The present invention relates to microprocessor development systems.
Nowadays microprocessor systems are frequently implemented as deeply embedded application specific systems, having a microprocessor core and with stored software routines and/or designed to run specific software routines. In order to remove errors and debug the system designed, microprocessor development systems are employed, which allow a technique called in-circuit emulation or in-circuit debug to enable the hardware and software designs to be debugged together by giving access to the state of the microprocessor and the progress of execution of the software program running on the microprocessor. Typically, this is realised by a special program, sometimes called a debug monitor, which runs on the microprocessor and is loaded into the microprocessor to interface to a debug or development system running on a host computer and to provide functions for accessing registers and memory of the microprocessor. Resources are provided for the debug monitor or program and host computer to use, such as reserved areas of program memory to hold the monitor program code and data memory for holding data transfer between the host and target system. The monitor program is executed by the microprocessor entering a special state and provides operations such as register and memory interrogation and modification.
The disadvantages with the traditional debug monitor technique is that space must be reserved for the monitor program in the target systems memory map, and space must be reserved for data used during transactions between the host computer system and the target system. The extra memory required to implement the traditional debug monitor approach is significant, and increases system cost.
In another technique for microprocessor development, which in general avoids the cost of implementing monitor programs in the target processor, known as a serial scan technique, a serial scan interface is provided to clock data into and out of the target system one bit at a time. The microprocessor""s registers are coupled together in series to form one or more test scan/chains which can be accessed by the external host to load test data and to read out the results in a serial manner. This permits the complete workings of the microprocessor to be observed. Most access to memory and peripherals can be achieved using the scan interface since control over the microprocessor buses is possible by coercing the state of the microprocessor via its registers.
Whilst the serial scan technique does not have the memory overhead of the monitor program technique, it can prove problematic for access to certain types of memory and peripherals:
i) When in debug mode all processor operations occur at the speed of the debug clock which is typically much lower the normal clock. Certain peripherals need to be accessed at full speed and are thus not accessible when in debug mode.
ii) When memories are shared between processors a protocol is defined that controls accesses to this memory from either processor. Support of this protocol in debug mode and at debug speeds can be complex or even impossible to achieve.
This invention applies to a serial scan technique for debugging a target processor. The basis of the invention is to employ a small, temporary, target processor monitor program to perform memory and peripheral accesses under control of the debugging host computer system. This monitor program is downloaded into the target processor via a scan chain, and does not require reservation of part of the target processor memory map.
Accordingly, the present invention provides in a processor including in-circuit emulation means comprising one or more scan chains of serially connected registers coupled to interface means for access by an external host, a method of carrying out a debug procedure, the method comprising:
1. providing a host computer system, the host computer system carrying out a debug procedure with said scan chains, and interrupting such debug procedure for access to a peripheral or memory mapped device,
2. the host computer system copying an area of memory of the processor and writing into said area of memory a program for reading and/or writing data at a specified location, (which location corresponds to a memory mapped area for peripheral access), and
3. the host computer causing said processor to run said program, and then to return to said debug procedure in which data from said specified location may be read to said host computer system.
Nowadays microprocessor systems are frequently implemented as embedded systems having a microprocessor core and with stored software routines and/or designed to run specific software routines. Some or all of the peripherals of the system are commonly incorporated in a single integrated circuit (IC). In order to remove errors and debug the system design, microprocessor development systems are employed, which generally allow a technique called in-circuit emulation or in-circuit debug to enable the hardware and software designs to be debugged together by giving access to the state of the microprocessor, as part of the hardware design, and the progress of execution of the software program running on it. Typically, this is realised by a special program, sometimes called a debug monitor, which runs on the microprocessor and is loaded into the microprocessor to interface to a debug or development system running on a host computer and provide functions for accessing registers and memory of the microprocessor system. Resources are provided for the debug monitor program and host computer to use, such as reserved areas of program memory to hold the monitor program code and data memory for holding data transfer between the host and target system. The monitor program is executed by the microprocessor entering a special state and provides operations such as register and memory interrogation and modification. Special provision must be made for the monitor program to execute, including program and data memory.
The disadvantages of this method are that it requires program memory resources (either RAM or ROM) to be provided in the system to hold the monitor program. If ROM is provided, this causes a reduction in the available program memory space for the application program. If RAM is provided, more RAM than otherwise will be required. In some systems this may mean that RAM will need to be provided where otherwise it would not.
In a deeply embedded application, such as a microprocessor which is a core element in an integrated circuit, it is an undesirable additional cost to provide memory resources to implement a monitor program. Access for debug software running on a deeply embedded microprocessor can be provided by means of a serial scan interface: that is by clocking data into and out of the system one bit at a time. In this serial scan method, known as ScanICE (trade mark), registers are provided throughout the microprocessor, coupled together in series to form a test scan chain which can be accessed by an external host to load test data into the scan chain and to read out the results. This permits the complete workings of the microprocessor to be observed. The main advantage of this serial scan method is that the test scan chain is used to retrieve the entire state of the microprocessor without the need for a monitor program to provide access to the internal registers. The serial scan method can be used to access memory mapped devices, slow memory, off-chip interfaces and so on. Specially designed hardware interfaces are designed into the system, which are controlled by the scan control logic. The scan control uses its complete access to all of the microprocessor""s control signals to control the interface logic using successive scanned vectors. However, this method is very complex, requires a lot of additional logic and may be very difficult to use in mixed memory systems. Sometimes it is not economical or even possible to implement a hardware scan interface to a microprocessor peripheral in a system in this way.
A technique known as a xe2x80x9cmicromonitorxe2x80x9d has been devised as a modification of the serial scan method to simplify memory access. In this a small program is downloaded into the processor""s program memory to perform memory accesses using the normal microprocessor mode of operation (rather than using scan registers to control the memory interface). In this method, a quantity of program RAM and of data RAM is read by the debug system, and stored elsewhere, i.e. backed-up. A very small program is loaded, using serial scanning, into this available program RAM space after having read and backed up the previous contents. Using the available data RAM space as a transfer data buffer, the program is used to access the memory or peripheral by returning the microprocessor to its normal running state executing instructions at the addresses of the available quantity of program RAM. Once the data transfer is complete, the backed-up data and program RAM contents are loaded back into the quantity of RAM and execution can continue normally. Hence the need for complex logic is reduced. However, this method relies on there being some accessible program RAM which is writable, because it is still necessary to read portions of the microprocessor""s data and program into the debugging system and to store them while the memory is used for the requirements of the micromonitor. Many embedded systems only contain ROM for program memory, so there is no possibility of downloading a micromonitor into normal RAM.
The basis of the present invention is to provide in a microprocessor or other processor, particularly an embedded processor core, a set of registers which can be loaded with program instructions from a test scan chain in the serial scan mode, and thereafter accessed by the processor for executing, in a normal manner, a short sequence of code.
Thus, the advantage of the xe2x80x9cmicromonitorxe2x80x9d approach described above is preserved while permitting use of the xe2x80x9cmicromonitorxe2x80x9d approach where no program RAM is available.
Accordingly, the present invention provides in a first aspect a processor including in-circuit emulation means comprising one or more chains of serially connected registers coupled to interface means for access by an external host to enable a serial scan procedure to be carried out, one such chain including a set of serially coupled registers for storing one or more processor instructions read into set of registers through the interface means, and the processor including address means, for addressing program memory, coupled to said set of registers for addressing the set of registers, and means for reading the processor instructions in the set of registers to an instruction register of the processor.
In a second aspect, the invention provides a method of in-circuit emulation for a processor comprising:
1) providing in the processor one or more chains of serially connected registers coupled to an interface means, one of said one or more chains including a set of serially coupled registers, such register set being coupled to the address and data buses of the processor,
2) feeding to the register set, through said interface means and said one scan chain, one or more processor instructions,
3) directing the processor to address the register set via its address bus, and to fetch on its data bus, the instruction stored therein and to carry out the instruction.
As preferred, the means for reading the processor instructions comprises a multiplexor arranged to receive the information in the set of registers at one input and the information from program memory at another input, the inputs being selected by a debug mode control signal. This permits the addressing of the registers by a range of addresses within the normal program memory address range, and for the information provided by the program memory when such address are asserted to be deselected.
Thus, the invention provides a xe2x80x9cregister filexe2x80x9d within the processor which can be loaded using the scan interface, and provides a special mode of operation substituted for normal program memory access as the source for fetched instruction and hence hold a micromonitor program.
The invention is implemented by embedding a set of registers within the processor. As preferred, the registers are arranged as a register file with a word width the same as the instructions of the processor, and a few words deep. Words of data from the register file can be read one at a time by applying an address, which is derived from the normal program address range of the microprocessor. The register file data output is multiplexed with the normal program instruction read data. The multiplexer is controlled by a debug control logic signal. Thus, from the microprocessor""s point of view the file appears to be a small block of program read only memory which is only selected during debug operations. The register file is loaded with a new micromonitor program by scanning data into it using the serial scan interface. The register file can either be attached to the scan chain of the rest of the microprocessor or it can be connected in a special scan chain of its own. The serial scan control logic controls the data loading procedure.